1. Field of the Invention
The present invention relates to an IC memory device such as AND flash memory, and relates particularly to an IC memory device such as AND flash memory having a plurality of AND flash memory chips packaged in a single package.
2. Description of the Related Art
FIG. 12 is a typical block diagram of an IC memory device 100 comprising a plurality of AND flash memory chips in a multiple chip package. In the example shown, the IC memory device 100 comprises four AND flash memory chips (simply "memory chips" below) 101-104 packaged in a single AND flash memory device. Each memory chip 101-104 has 528-byte sectors.
Chip enable signals CEa# to CEd#, serial clock signals SCa to SCd, command enable signals CDEa# to CDEd#, write enable signals WEa# to WEd#, and output enable signals OEa# to OEd# are applied respectively to memory chips 101-104. The memory chips 101-104 are also connected to corresponding data buses a to d, which are used for command input and data input/output. It may be apparent that the IC memory device 100 therefore requires sufficient control signal lines and data buses to handle the signal I/O requirements of these four memory chips 101-104. It should be noted that the "#" symbol used above indicates signal level inversion with the corresponding signal being active low.
FIG. 13 is a sequence diagram showing a sequential data read operation from the same sector address in each of the memory chips 101-104 in the above IC memory device 100. As shown in FIG. 13, when an external device applies a read command to the first of the plural memory chips 101-104 in the IC memory device 100, the sector address for the read operation is applied to the addressed memory chip, specifically memory chip 101 in the present example. Because each sector is 528 bytes in this IC memory device 100, data is read sequentially from column address 0 to column address 527 at the specified sector address of the memory chip 101, and output from data bus a.
When a read command for the next memory chip in this group of four memory chips 101-104 is then applied from an external source, the sector address of the read operation is input to memory chip 102. The IC memory device 100 thus reads data sequentially from column address 0 to column address 527 at the specified sector address, and outputs to data bus b. This sequence of steps is simply repeated to read and output data continuously from the same sector address in each of the memory chips 101-104.
The operations for continuously erasing or writing data to the same sector address in each of the memory chips 101-104 are substantially identical to the sequence and process described above except that a write or erase command is applied and the data is written to or erased from the specified column addresses. Further description thereof is thus omitted below.
To sequentially read, write, or erase the same sector address in each of the memory chips 101-104 of a conventional IC memory device comprising a plurality of AND flash memory chips in a multiple chip package, it is therefore necessary to individually apply a specific command and sector address to each of the memory chips 101-104. This need to individually address each of a plurality of memory chips to continuously read, write, or erase the same sector address in each memory chip necessarily increases the total time required for the read, write, or erase operation.
There is therefore a need for an IC memory device whereby the time required to continuously read, write, or erase the same sector address in a plurality of memory chips can be reduced.